/************************************************** versys eda example-----**** ram.v ****------------- ----------Verilog module of static ram------------- Copyright (c) 1996-2009, by all Contributions. All rights reserved. *************************2009/06/22 lexim,inc.*****/ module ram(addr, enable, readwr, data); input [7:0] addr; input enable, readwr; inout [15:0] data; reg [15:0] ramdata [255:0]; assign data = (enable & !readwr) ? ramdata[addr] : 16'bz; always @(addr or enable or readwr or data) begin if (enable & readwr) ramdata[addr] = data; end endmodule